Stacking field-effect transistors (FETs) in the vertical direction gives an additional dimension for complementary metal-oxide-semiconductor (CMOS) area scaling. However, it is very challenging to stack planar FETs.
Vertical field effect transistors (VFETs) on the other hand have a unique structure that can help the stacking process. Namely, as opposed to planar CMOS devices, VFETs are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. The gate runs vertically alongside the vertical fin channel. VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.
Accordingly, stacked VFET designs and techniques for formation thereof would be desirable.